1. Field of the Invention
The invention relates to a semiconductor device and a data processing system using the semiconductor device, and more particularly, to a semiconductor device including crown-shaped capacitors as compensation capacitance elements and a date processing system using the semiconductor device.
2. Description of the Related Art
In semiconductor devices, such as DRAM, there is an attempt to proceed with low voltage operating power supply of circuit elements, to cope with the reduction of electric power consumption. Dealing with the low voltage operation, a power supply voltage, which is supplied from an external power supply, is generally dropped to a voltage used inside semiconductor devices, and then supplied to the circuit elements.
Accompanying to a reduction of the operating power supply voltage, influence of a fluctuation of the power supply voltage to circuit operation is increased, and thus a stable supplying of the power supply voltage is critical. Therefore, a technique is known in which a compensation capacitance element is arranged between a wiring for supplying a power supply potential and a wiring for supplying a grounding potential (see JP2010-067661 A).
In addition, with respect to the invention, a technique is also known in which capacitors used in memory cells of DRAM are formed in a crown shape to use as electrodes both of internal and outer walls of lower electrodes, and a support film (support body) is provided to prevent the lower electrodes from being toppled (i.e., collapsing) during fabrication processes (see JP2003-297952 A).
By forming the capacitors in such a crown shape, electrostatic capacity thereof can be increased without increase of a footprint.
In semiconductor devices with relation to DRAM, when a compensation capacitance element is provided, capacitors having the same structure as that of capacitors used in memory cells can be arranged as a compensation capacitance element (see JP2010-067661 A).
Instead of providing planar-shaped capacitors, the capacitors having such a three-dimensional structure are used, such that a footprint of the compensation capacitance element can be reduced.
As stated above, in recent DRAMs, crown-shaped capacitors having a large electrostatic capacity are used in memory cells, accompanying to development of downscaling. As a result of intensive studies on a case in which crown-shaped capacitors are used for memory cells and a compensation capacitance element, the present inventor has found that the following problems would be caused.
In recent crown-shaped electrodes downscaled, the electrodes are supported therebetween by a support film structure as disclosed, for example, in JP2003-297952 A, such that collapsing of the electrodes can be prevented during fabrication processes. In this time, a ring shape region (i.e., a guard ring region) is provided to surround a perimeter of a region in which capacitors are disposed, and the support film connects the guard ring region with each of capacitors, and thereby supporting the capacitors. In this case, it is necessary to prepare a region required to arrange the guard ring region. When a plurality of compensation capacitance elements are arranged using the downscaled crown-shaped electrodes as described above, a guard ring region needs to be arranged on each block (hereafter, referred to as a “compensation capacitance block”) in which each of compensation capacitance elements is disposed, and thereby disturbing reduction of a footprint on a semiconductor chip.
Therefore, the present inventor has studied on a structure in which a support film structure connecting the capacitors to each other only supports the capacitors, without providing a guard ring region.
When crown-shaped capacitors are arranged as the compensation capacitance element, if about 10,000 capacitors are arranged in one rectangular compensation capacitance block in the same arrangement as that of the memory cell regions, collapsing of the capacitors can only prevented by connecting adjacent electrodes by the support film, without providing a guard ring region.
In the memory cell region, capacitors more than that of the compensation capacitance block are arranged in one integrated region (i.e., a memory cell mat region), and thus, collapsing of the capacitors can similarly prevented by connecting adjacent electrodes by the support film.
In this case, depending on a voltage applied to a circuit to be connected, a higher voltage than that of capacitors used as the memory cells may be applied to the compensation capacitance element. When forming in the same shape as that of the capacitors of the memory cell region, a dielectric breakdown in a dielectric film interposed between lower and upper electrodes would be concerned, and thus, the voltage applied to each of capacitors needs to be reduced. Therefore, a plurality of compensation capacitance blocks are connected in series, such that a voltage applied to each of capacitors disposed in one compensation capacitance block can be reduced.
Also, the present inventor has studied on a case in which a plurality of compensation capacitance blocks are arranged to be connected in series without providing a guard ring region. As a result, the present inventor has found that a cavity (void) is formed in an interlayer insulating film filled between compensation capacitance blocks.
The reason is that an aspect ratio in recent crown-shaped electrodes downscaled is increased, and when the interlayer insulating film, such as silicon oxide film, covering the capacitors is formed by CVD method, the vicinity of upper portions of the electrodes is obstructed.
If the cavity is remained in the interlayer insulating film, a short circuit between adjacent contact plugs is generated through the cavity, or strength of the interlayer insulating film is decreased. Therefore, the cavity formation causes the decrease in fabrication yield.
When the compensation capacitance blocks are sufficiently spaced to each other, the cavity formation in the interlayer insulating film can be inhibited, but an area required arranging the compensation capacitance element is increased and thereby disturbing reduction of the area on a semiconductor chip.
Therefore, it is difficult to use the compensation capacitance element having crown-shaped capacitors in conventional methods.